The invention relates generally to data processing apparatus and methods, and in particular to the selection and collection of data bits from a data word.
During the processing of instructions in a data processing apparatus, it is common to instruct the apparatus to effect a program flow modification according to the value of a selected group of data bits in a stored or recently generated data word. Typically, it is desired to employ the selected bits to determine the address of a next program instruction for the apparatus. This is typically known as a computed GO TO instruction. While it is possible to search out the selected bits using software or firmware (microcode) programs, it is preferable to implement a hardware circuitry to increase throughput performance; however logic circuitry may increase faster than linearly with the number of bits being selected and may not operate satisfactorily under severe time constraints.
One such circuit is described in Calcagmo et al, U.S. Pat. No. 4,009,468. This logic network, designated a data concentrator, presents on its output lines, a number of bits selected from an input word having some larger number of bits. The Calcagmo circuitry has two operating sections, an enabling section and a performing section as described in the patent. The resulting circuitry requires a significant number of logic elements, especially for the performing section selection circuitry which provides for the selected bit outputs.
It is therefore an object of the present invention to provide a high speed, low hardware requirement, logic network which can be employed in a bus data path for selecting from among the bits at its input in accordance with a control word, and providing those selected bits at its output. Other objects of the invention are to provide a bit selection apparatus and method for quickly enabling multi-way branching, byte selection, and one-way shifting. Further objects of the invention are a bit select apparatus and method which can be implemented in MOS technology.